Accession Number : ADD018139
Title : Low and High Minority Carrier Lifetime Layers in a Single Semiconductor Structure.
Descriptive Note : Patent, Filed 26 Jun 95, patented 28 May 96,
Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC
Personal Author(s) : Walker, Howard W ; Garcia, Graham A
Report Date : 28 May 1996
Pagination or Media Count : 4
Abstract : A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer and another layer of silicon dioxide on a layer of high minority carrier lifetime silicon of a bulk silicon device wafer. The silicon dioxide layers are placed in contact and annealed to form a bonded structure having an annealed layer of silicon dioxide. The layer of bulk silicon is then thinned. The thinned layer of bulk silicon and the annealed silicon dioxide layer are patterned by photolithography to form mesas of high minority carrier lifetime silicon and to expose regions of low minority carrier lifetime silicon on the bonded structure.
Descriptors : *SEMICONDUCTORS, *WAFERS, *PATENTS, *SILICON ON SAPPHIRE, ANNEALING, LAYERS, SILICON DIOXIDE, CHARGE CARRIERS, INTEGRATED CIRCUITS, SILICON, BONDING, PHOTOLITHOGRAPHY, ATOMIC LAYER EPITAXY, SILICON ON INSULATOR
Subject Categories : Solid State Physics
Distribution Statement : APPROVED FOR PUBLIC RELEASE