Accession Number : ADD018464

Title :   Decoder Circuit for Generating a System Clock Signal Phase Locked to a Range Tone Signal.

Descriptive Note : Patent, Filed 13 May 94, patented 12 Sep 95,

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Cirineo, Anthony

Report Date : 12 Sep 1995

Pagination or Media Count : 14

Abstract : A decoder circuit for receiving a video input signal which includes Manchester coded data bits and a range tone component having a frequency of about 102.6 kilohertz. A phase lock loop circuit detects the presence of the 102.6 kilohertz range tone component and then generates a system clock signal which is phase locked to the range tone component of the video input signal. The system clock signal is provided to a clock generating circuit which generates a clock signal having four phases. The phase lock loop circuit also provides a logic signal which is supplied to a data detecting circuit allowing the data detecting circuit to convert the Manchester coded data bits to digital data bits.

Descriptors :   *ANALOG TO DIGITAL CONVERTERS, *DECODERS, *PATENTS, CIRCUITS, VIDEO SIGNALS, LOOPS, SIGNAL GENERATORS, PHASE LOCKED SYSTEMS

Subject Categories : Cybernetics
      Telemetry
      Radio Communications

Distribution Statement : APPROVED FOR PUBLIC RELEASE