Accession Number : ADD018701

Title :   Method for Fabricating Complementary Vertical Bipolar Junction Transistors in Silicon-On-Sapphire

Descriptive Note : Patent, Filed 3 Apr 95, patented 24 Jun 97

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Cartagena, Eric N ; Walker, Howard W

Report Date : 24 Jun 1997

Pagination or Media Count : 10

Abstract : A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ silicon island by epitaxially growing an N-type silicon layer on the N+ silicon island. Then, a P region is created in the N-type silicon layer. An N+ region created in the P region completes the NPN junction device. Similarly, a PNP junction device is formed by epitaxially growing a P-type silicon layer on the P+ silicon island. Then, an N region is created in the P-type silicon layer. A P+ region created in the N region completes the PNP junction device.

Descriptors :   *BIPOLAR TRANSISTORS, *PATENTS, *JUNCTION TRANSISTORS, *SILICON ON SAPPHIRE, LAYERS, FABRICATION, EPITAXIAL GROWTH, SUBSTRATES, SEMICONDUCTORS, VERTICAL ORIENTATION, OXIDES, N TYPE SEMICONDUCTORS, P TYPE SEMICONDUCTORS, PNP TRANSISTORS

Subject Categories : Electrical and Electronic Equipment

Distribution Statement : APPROVED FOR PUBLIC RELEASE