Accession Number : ADD018715

Title :   Method and Apparatus for Pre-Processing Inputs to Parallel Architecture Computers

Descriptive Note : Patent, Filed 23 Mar 95, patented 5 Aug 97

Corporate Author : DEPARTMENT OF THE NAVY WASHINGTON DC

Personal Author(s) : Kevorkian, Aram K

Report Date : 05 Aug 1997

Pagination or Media Count : 61

Abstract : A preprocessing method and preprocessor decompose a first problem belonging to a class of linear algebra problems comprising an input sparse symmetric matrix into a suite of subproblems. The preprocessor generates a suite of signals representing the information content of a permutation of the rows and columns of the sparse symmetric matrix. These signals are used to define a block-bordered diagonal form leading to a sparse Schur complement resolution wherein each subproblem corresponds to a perfect parallelism in the first problem. The preprocessor allocates the sub-problems to sub-processors in a network of parallel architecture computers. The subprocessors solve the subproblems concurrently and combine the results in a front end computer which outputs a solution to the first problem.

Descriptors :   *COMPUTER ARCHITECTURE, *PARALLEL PROCESSING, *PATENTS, INPUT, COMPUTERS, LINEARITY, SYMMETRY, SPARSE MATRIX, PERMUTATIONS, PREPROCESSING, LINEAR ALGEBRA

Subject Categories : Computer Hardware

Distribution Statement : APPROVED FOR PUBLIC RELEASE