Accession Number : ADP002332

Title :   The New Method of Implementation for Ternary Logic System,

Corporate Author : SHANGHAI INST OF RAILWAY TECHNOLOGY (CHINA) DEPT OF TELECOMMUNICATION

Personal Author(s) : Meng,L. ; Wei-Nan,G.

Report Date : MAY 1983

Pagination or Media Count : 5

Abstract : In various ternary logic systems, symmetric ternary logic system which satisfies lattice operation is most appropriate. A new method of implementation for ternary logic using COS/MOS circuits is put forward, only one circuit simple structure can constructs a ternary logic complete system. The paper also discusses the possibility of applying this circuit for the implementation of J-OR and J-AND operation. Thus, the implementation for ternary logic system can be greatly simplified. (Author)

Descriptors :   *Logic circuits, *Complementary metal oxide semiconductors, *Metal oxide semiconductors, *Gates(Circuits), *Symposia, Mathematical logic, Symmetry, Foreign technology, Circuits, China

Distribution Statement : APPROVED FOR PUBLIC RELEASE