Accession Number : ADP002334

Title :   Low Power 2-of-3-Valued CMOS Self-Checking Circuits,

Corporate Author : SHANGHAI INST OF RAILWAY TECHNOLOGY (CHINA) DEPT OF TELECOMMUNICATION

Personal Author(s) : Hu,M. ; Smith,K. C. ; Mouftah,H. T.

Report Date : MAY 1983

Pagination or Media Count : 6

Abstract : Two new schemes for the implementation of self-checking binary logic systems are proposed which utilizes low power 2-of-3-valued CMOS logic circuits. While 2-of-3-valued circuits are inherently ternary, only two of their three logic values are used in normal operation. The third (middle) logic value is used for self-checking and testing. To evaluate these circuits an open-short-conducting fault model for CMOS circuits is developed. All of the single faults in these circuits are studied and classified into four types, named mid-seeking, quasi-mid-seeking, mid-rejecting, and masked. The conclusions reached for 2-of-3-valued circuits in previous papers apply to these new circuits as well. Finally a comparison between implementation schemes is made on the basis of the size of the fault set each produces. (Author)

Descriptors :   *Logic circuits, *Complementary metal oxide semiconductors, *Test methods, Inverter circuits, Faults, Short circuits, Value, Checkout procedures, Operation, Self operation, Normality, Low power, Logic, Foreign technology, Circuits

Distribution Statement : APPROVED FOR PUBLIC RELEASE