
Accession Number : ADP002351
Title : A Quaternary Logic EncoderDecoder Circuit Design Using CMOS,
Corporate Author : CALIFORNIA UNIV DAVIS INTEGRATED CIRCUITS LAB
Personal Author(s) : Freitas,D. A. ; Current,K. W.
Report Date : MAY 1983
Pagination or Media Count : 6
Abstract : A binarytoquaternary encoder and quaternarytobinary decoder circuit pair is described as designed in a 5volt CMOS technology. These circuits communicate with logical currents. Using model parameter values for a standard 5micron polysilicon gate process technology and 10 microamp logical currents, we have simulated propagation delays of about 20 ns from binary encoder input to binary decoder output. With the encoder using scaledup logical currents and driving a 100 pF load on the decoder input to simulate communication between chips, we observe simulated worstcase delays of about 35ns. (Author)
Descriptors : *Coders, *Decoders, *Silicon, *Logic circuits, *Complementary metal oxide semiconductors, Gates(Circuits), Parameters, Value, Electric current, Input, Output, Value, Coupling(Interaction), Binary notation
Distribution Statement : APPROVED FOR PUBLIC RELEASE