Accession Number : ADP002376

Title :   A Method of Test Generation for Verification of Wiring Correctness,

Corporate Author : POZNAN TECHNICAL UNIV (POLAND) REGIONAL COMPUTER CENTER

Personal Author(s) : Bucholc,K.

Report Date : MAY 1983

Pagination or Media Count : 4

Abstract : The paper presents a method of test generation for any multiterminal wiring network, such as printed circuit board, computer backpanel wiring etc. The method is based on the minimization of the test generated by examining the correct network with computer-controlled tester. Three-valued algebra was used. In comparison with more straightforward algorithm based on the adjacency matrix, lower space complexity has been achieved - O(n) rather than O(sq. n). (Author)

Descriptors :   *Faults, *Detection, *Circuits, *Networks, *Terminals, *Test methods, *Symposia, Printed circuit boards, Wiring diagrams, Reduction, Computer applications, Poland

Distribution Statement : APPROVED FOR PUBLIC RELEASE