Accession Number : ADP002620

Title :   Yield Enhancement by Fault Tolerant Systolic Arrays,

Corporate Author : NORTHWESTERN UNIV EVANSTON IL DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE

Personal Author(s) : Kuhn,R. H.

Report Date : 1983

Pagination or Media Count : 8

Abstract : In this paper interstitial fault tolerance (IFT), a technique for incorporating fault tolerance into systolic arrays in a natural manner, is discussed. IFT can be used for reliable computation or for yield enhancement. Here the author compares IFT used for yield enhancement to Wafer Scale Integration (WSI) techniques. Previous WIS techniques for yield enhancement have been proposed only for linear processing element arrays. IFT is effective for both linear and two dimensional arrays. Results of Monte Carlo yield simulation of IFT are presented. (Author)

Descriptors :   *Fault tolerant computing, *Methodology, Arrays, Monte carlo method, Computations, Yield

Distribution Statement : APPROVED FOR PUBLIC RELEASE