Accession Number : ADP008011
Title : Buried Interconnect Structure for Symmetric SEEDs,
Corporate Author : AT AND T BELL LABS MURRAY HILL NJ
Personal Author(s) : D'Asaro, L. A. ; Chirovsky, L. M. ; Kopf, R. F. ; Pearton, S. J.
Report Date : JUL 1992
Pagination or Media Count : 3
Abstract : The mesa structure previously published for S-SEED arrays has a number of disadvantages for future integration with electronic circuits on the same chip. These problems arise from the large (=1 um) height of the mesas: (1) the angle on the sides of the mesas takes up valuable real estate, (2) the metallization of the mesa sidewall for interconnect can introduce a yield problem because of difficulty in covering, (3) the etching of the sidewall is a critical step which requires accurate control to expose the buried N-layer for contacting, (4) the lithography resolution is degraded by the large topography, and (5) the mesa sidewall presents a surface where minority carriers recombine and thereby reduce the photocurrent collection efficiency.
Descriptors : *OPTICAL CIRCUITS, ARRAYS, COLLECTION, CONTROL, COVERINGS, EFFICIENCY, ELECTRONICS, ETCHING, HEIGHT, INTEGRATION, LAYERS, LITHOGRAPHY, RESOLUTION, STRUCTURES, SURFACES, TOPOGRAPHY, YIELD, PIN DIODES.
Subject Categories : Electrooptical and Optoelectronic Devices
Distribution Statement : APPROVED FOR PUBLIC RELEASE