Accession Number : ADP008658

Title :   An Optical Respite from the Von Neumann Bottleneck,

Corporate Author : AT AND T BELL LABS HOLMDEL NJ

Personal Author(s) : Dickinson, Alex

Report Date : 22 MAY 1992

Pagination or Media Count : 4

Abstract : The high end of microprocessor performance is currently dominated by Reduced Instruction Set Computer (RISC) architectures. These machines execute one or more instructions per clock cycle. A processor such as the i860 runs with a 40MHz clock - requiring that on average an instruction must be delivered to the CPU every 25nS. With DRAm access times currently at around 100nS, timely instruction delivery has become a critical constraint on processor speed. The primary tool for dealing with this problem is the use of fast cache memories local to the processor. These caches make use of both temporal locality (if the processor just accessed a location, it will probably do it again soon) and spatial locality (if the processor just accessed a location, it will probably access a nearby one soon). The caches are implemented in fast static RAM on the processor die. If an item is in cache (a 'hit') it may typically be retrieved within a single processor cycle (the hit time). If an item is not in cache (a 'miss') it must be retrieved from the off-chip main memory at a considerable cost in time. This later time is referred to as the miss penalty.

Descriptors :   *RELIABILITY(ELECTRONICS), *OPTICAL DATA, *PATHS, MICROPROCESSORS, INSTRUCTIONS, PROBLEM SOLVING, ACCESS TIME.

Subject Categories : Computer Hardware
      Electrooptical and Optoelectronic Devices

Distribution Statement : APPROVED FOR PUBLIC RELEASE