Accession Number : ADP008659
Title : Dual Scale Topology Opto-Electronic Processor (D-STOP): Comparative Analysis and Technological Feasibility,
Corporate Author : CALIFORNIA UNIV SAN DIEGO LA JOLLA DEPT OF ELECTRICAL AND COMPUTER ENGINEERIN G
Personal Author(s) : Krishnamoorthy, A. V. ; Ford, J. E. ; Marsden, G. C. ; Yayla, G. ; Esener, S. C.
Report Date : 22 MAY 1992
Pagination or Media Count : 4
Abstract : A variety of applications in artificial neural networks, interconnection networks, artificial intelligence, relational databases, and numerical processing require parallel, large scale implementations of matrix-algebraic architectures. Existing VLSI implementations of these architectures are restricted in terms of their parallelism and bandwidth due to their inherent connectivity, pin-out, power dissipation, and crosstalk limitations. On the other hand, existing optical matrix-vector architectures suffer from limited SLM throughput and accuracy as well as limited functional flexibility. In the following sections we describe and analyze the Dual-Scale Topology Opto-Electronic Processor (D-STOP) which alleviates these limitations, and discuss its feasibility for a near-term implementation.
Descriptors : *ELECTROOPTICS, *COMPUTER ARCHITECTURE, FEASIBILITY STUDIES, COMPARISON, VERY LARGE SCALE INTEGRATION, DATA PROCESSING, MATRICES(MATHEMATICS), ALGEBRA.
Subject Categories : Electrooptical and Optoelectronic Devices
Distribution Statement : APPROVED FOR PUBLIC RELEASE